1. Field of Invention
The present invention relates to a field effect transistor and more particularly, to a field effect transistor having a ferroelectric gate film, which is used in a nonvolatile memory or the like.
2. Description of Prior Art
FIG. 4 is a schematic sectional view showing a structure of a conventional field effect transistor having a ferroelectric gate film (referred to as a MFSFET (Metal Ferroelectric Semiconductor Field Effect Transistor) hereinafter), which is used in a nonvolatile memory or the like.
Referring to FIG. 4, reference numeral 1 designates a P-type silicon substrate, reference numerals 2a and 2b designate N-type impurity diffused layers serving as source and drain regions, which are formed on a surface of the silicon substrate 1 at a predetermined interval, reference numeral 3 designates a ferroelectric gate film provided on a channel region 2c sandwiched by the N-type impurity diffused layers 2a and 2b, reference numeral 4 designates a gate electrode formed on the ferroelectric gate film 3, reference numerals 5a and 5b designate source/drain electrode wirings connected to the N-type impurity diffused layers 2a and 2b, respectively, and reference numeral 6 designates an interlaminar insulating film for insulating from each other the gate electrode 4 and the source/drain electrode wirings 5a and 5b. In this structure, the gate electrode 4 and the ferroelectric gate film 3 provide a so called MFS structure. Furthermore, it is possible to interpose a buffer film between the gate electrode 4 and the ferroelectric gate film 3 or between the ferroelectric gate film 3 and the channel region 2c.
Although as a ferroelectric material, ABO.sub.3 type (A, B: metal element) such as PZT, PLZT, PbTiO.sub.3, BaTiO.sub.3, which has the perovskite structure is generally used, a material showing ferroelectricity may be used. Besides, halogen compounds such as BaMgF.sub.4, NaCaF.sub.3, K.sub.2 ZnCl.sub.4 or chalcogen compounds such as Zn.sub.1-x Cd.sub.x Te, GeTe or Sn.sub.2 P.sub.2 S.sub.6 may be used.
The ferroelectric substance in the MFSFET has P-E hysteresis characteristics shown in FIG. 5. Referring to FIG. 5, a voltage which applies an electric field E.sub.sat to the ferroelectric substance is assumed to be V.sub.max (&gt;0). When a voltage +V.sub.max is applied to the gate electrode 4 of the MFSFET shown in FIG. 4, the ferroelectric gate film 3 is polarized to a state of A, whereby a channel 2c is formed. Thereafter, even if the voltage of the gate electrode 4 is reduced to 0, polarization of the film 3 becomes a state of B, which means that a residual polarization known as spontaneous polarization remains in the ferroelectric gate film 3 and the channel 2c still exists. Meanwhile, when a voltage -V.sub.max is applied to the gate electrode 4 (or the voltage +V.sub.max is applied to the substrate 1), the ferroelectric gate film 3 is polarized to a state of C. When the voltage is set to 0, polarization of the film 3 becomes a state of D. In this case, the channel 2c is not formed.
However, in the MFSFET, the ferroelectric gate film is formed by directly laminating an oxide ferroelectric substance such as PZT or a fluoride ferroelectric substance such as BaMgF.sub.4 on the silicon substrate, so that it does not reach a level of practical use.
More specifically, when the oxide ferroelectric substance is used, the following problems (1) to (3) are generated.
(1) When the oxide ferroelectric substance is laminated on the silicon substrate, an unnecessary film such as SiO.sub.2 is generated between the ferroelectric substance and the silicon substrate. In order to reverse polarization of the ferroelectric substance, it is necessary to generate an electric field in the ferroelectric substance by applying a voltage between the gate electrode and the silicon substrate. Incidentally, when the unnecessary film is formed between the ferroelectric substance and the silicon substrate as described above, a laminated capacitor structure is provided. Therefore, in order to generate a sufficient electric field in the ferroelectric substance, it is necessary to increase an applied voltage. As a result, a trap level is increased and then electron is trapped at an interface between the unnecessary film and the silicon substrate or in the unnecessary film. Consequently, transistor characteristics in itself can not be obtained.
(2) Processing at high temperature is necessary. More specifically, a crystallization temperature of the oxide ferroelectric substance is generally high. For example, PZT is crystallized at approximately 600.degree. C. or more, which is a big problem in a case where Pb or the like is diffused into the silicon substrate and matching with the silicon process is considered.
(3) Its crystal structure is complicated, causing some problems. More specifically, since the oxide ferroelectric substance has to be mixed with three elements or more, its crystal structure becomes complicated, making a film forming process difficult. In addition, if reversal of polarization is often repeated, crystallizability could deteriorate.
Meanwhile, when the fluoride ferroelectric substance is used, although the above problem (1) is not generated, the problems (2) and (3) are still unsolved.
3. Description of the Related Art
In order to solve the above problems, the inventor of the present invention has proposed a technique in which a IV-VI group compound ferroelectric substance, represented by GeTe is used as the ferroelectric substance in Japanese Patent Application No. 306561/1991.
The IV-VI group compound ferroelectric substance, represented by GeTe shows polarization in the direction (111). As an LSI (Large Scale Integrated Circuit) substrate such as a nonvolatile memory device, a silicon substrate having a crystalline orientation (100) on a surface thereof is mainly used at present. When the IV-VI group compound ferroelectric substance, represented by GeTe is used, it is preferable that an orientation film of the ferroelectric substance is formed, with a crystalline orientation (111), on the surface of the silicon substrate having a crystalline orientation (100), with regard to matching with the present process technique. This is because when the ferroelectric gate film is formed with a crystalline orientation (111), ferroelectricity, when residual polarization exists or coesive electric field is applied, is superior to that when the ferroelectric gate film is formed with a crystalline orientation (100). Consequently, an operation voltage of the MFSFET is reduced and a process margin can be increased.
However, in the technique disclosed in the Japanese Patent Application No. 306561/1991, since a buffer film comprising CaF.sub.2 or the like is interposed between the silicon substrate and the ferroelectric gate film, it is difficult to form an orientation film comprising the IV-VI group compound ferroelectric substance with a crystalline orientation (111), on a surface of crystalline orientation (100) of a silicon substrate.
More specifically, since a lattice constant of CaF.sub.2 matches well to that of silicon in the silicon substrate and then mismatching in lattice constant is too small, approximately 0.6%, the film is likely to be influenced by the silicon of the silicon substrate which is placed under the CaF.sub.2, so that the orientation film is formed with a crystalline orientation (100). Therefore, although the IV-VI group compound ferroelectric substance shows polarization in the direction (111), the film has a crystalline orientation (100).